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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
The MPC990/991 is a 3.3V compatible, PLL based ECL/PECL clock driver. The fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC990/991 makes the device ideal for Workstation, Mainframe Computer and Telecommunication applications. The MPC990 and MPC991 devices are identical except in the interface to the reference clock for the PLL. The MPC990 offers an on-board crystal oscillator as the PLL reference while the MPC991 offers a differential ECL/PECL input for applications which need to lock to an existing clock signal. Both designs offer a secondary single-ended ECL clock for system test capabilities.
MPC990 MPC991
LOW VOLTAGE PLL CLOCK DRIVER
* * * * * * *
Fully Integrated PLL Output Frequency Up to 400MHz ECL/PECL Inputs and Outputs Operates from a 3.3V Supply Output Frequency Configurable TQFP Packaging 50ps Cycle-to-Cycle Jitter
The MPC990/991 offers three banks of outputs which can each be FA SUFFIX programmed via the the four fsel pins of the device. There are 16 different 52-LEAD TQFP PACKAGE output frequency configurations available in the device. The CASE 848D-03 configurations include output ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and 4:3:2. The programming table in this data sheet illustrates the various programming options. The SYNC output monitors the relationship between the Qa and Qc output banks. The output pulses per the timing diagrams in this data sheet signal the coincident edges of the two output banks. This feature is useful for non binary relationships between output frequencies (i.e., 3:2 or 4:3 relationships). The Sync_Sel input toggles the Qd outputs between sync signals and extensions to the Qc bank of outputs. The MPC990/991 provides a separate output for the feedback to the PLL. This allows for the feedback frequency to be programmed independently of the other outputs allowing for unique input vs output frequency relationships. The fselFB inputs provide 6 different feedback frequencies from the QFB differential output pair. The MPC990/991 features an external differential ECL/PECL feedback to the PLL. This external feedback feature allows for the MPC991's use as a "zero" delay buffer. The propagation delay between the input reference and the output is dependent on the input reference frequency. The selection of higher reference frequencies will provide near zero delay through the device. The PLL_En, Ref_Sel and the Test_Clk input pins provide a means of bypassing the PLL and driving the output buffers directly. This allows the user to single step a design during system debug. Note that the Test_Clk input is routed through the dividers so that depending on the programming several edges on the Test_Clk input will be needed to get corresponding edge transitions on the outputs. The VCO_Sel input provides a means of recentering the VCO to provide a broader range of VCO frequencies for stable PLL operation. If the frequency select or the VCO_Sel pins are changed during operation, a master reset signal must be applied to ensure output synchronization and phase-lock. If the VCO is driven beyond its maximum frequency, the VCO can outrun the internal dividers when the VCO_Sel pin is low. This will also prevent the PLL from achieving lock. Again, a master reset signal will need to be applied to allow for phase-lock. The device employs a power-on reset circuit which will ensure output synchronization and PLL lock on initial power-up.
2/97
(c) Motorola, Inc. 1997
1
REV 2
MPC990 MPC991
VCCO
fsel0
fsel1
fsel2
39 Qb3 Qb3 VCCO Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3 SYNC_Sel VCO_Sel 40 41 42 43 44 45 46 47 48 49 50 51 52 1
38
37
36
35
34
33
32
31
30
29
28
fsel3 27 26 25 24 23 22 21 Qc1 Qc1 Qc0 Qc0 VCCO Qd1 Qd1 Qd0 Qd0 VCCO QFB QFB VCCA 20 19 18 17 16 15 14 13 Ext_FB Qc /2 /4 /4 /6 /6 /6 /8 /8 /8 /8 /6 /6 /8 /8 /8 /8
Qb2
Qb2
Qb1
Qb1
Qb0
Qb0
Qc2 11 VCCI /2 /2 /4 /2 /6 /4 /4 /6 /2 /8 /4 /6 /6 /6 /8 /8
MPC990/ MPC991
2
3
4
5
6
7
8
9
10
PLL_En
Ref_Sel
GNDI
MR
Test_Clk
fselFB2
fselFB1
fselFB0
Figure 1. 52-Lead Pinout (Top View) FUNCTION TABLE 1
INPUTS fsel3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 fsel2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 fsel1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 fsel0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Qa /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /4 /4 /4 /6 /6 /8 OUTPUTS Qb
MOTOROLA
2
xtal1 (990) ECL_CLK (991) xtal2 (990) ECL_CLK (991)
Ext_FB
Qc2 12
TIMING SOLUTIONS BR1333 -- Rev 6
MPC990 MPC991
FUNCTION TABLE 2
fselFB2 0 0 0 0 1 1 1 1 fselFB1 0 0 1 1 0 0 1 1 fselFB0 0 1 0 1 0 1 0 1 QFB /2 /4 /6 /8 /8 /16 /24 /32
FUNCTION TABLE 3
Control Pin PLL_En VCO_Sel Ref_Sel MR SYNC_Sel Logic `0' Enable PLL fVCO xtal or ECL/PECL -- SYNC Outputs Logic `1' Bypass PLL fVCO/2 Test_Clk Reset Outputs Match Qc Outputs
VCO_Sel PLL_En Ref_Sel Test_Clk ECL_Clk ECL_Clk
(Pulldown) (Pulldown) (Pulldown) (Pulldown)
Qa0 Qa0 Qa1 Qa1 MPC991 PHASE DETECTOR LPF VCO Qa2 Qa2 Qa3 Qa3 Qb0 Qb0 Qb1 Qb1 FREQUENCY GENERATOR Qb2 Qb2 Qb3 Qb3 Qc0 Qc0 Qc1 Qc1 Qc2 Qc2
Ext_FB Ext_FB MR
(Pulldown)
fsela0:3
(Pulldown)
SYNC
fselFB0:2
(Pulldown)
SYNC_Sel
(Pulldown)
Qd0 Qd0 Qd1 Qd1 QFB QFB
Xtal Osc MPC990 NOTE: ECL_Clk, Ext_FB have internal pulldowns, while ECL_Clk, Ext_FB have external pullups to ensure stability under open input conditions.
Figure 2. MPC990/991 Logic Diagram
TIMING SOLUTIONS BR1333 -- Rev 6
3
MOTOROLA
MPC990 MPC991
1:1 Mode Qa
Qc Sync (Qd) 2:1 Mode Qa VCC
Qc
Sync (Qd)
3:1 Mode Qa
Qc
Sync (Qd)
3:2 Mode Qa
Qc
Sync (Qd)
4:3 Mode Qa
Qc
Sync (Qd)
Figure 3. Timing Diagrams
MOTOROLA
4
TIMING SOLUTIONS BR1333 -- Rev 6
MPC990 MPC991
ECL DC CHARACTERISTICS (TA = 0 to 70C, VCCA = VCCI = VCCO = 0V, GNDI = -3.3V 5%, Note 1.)
0C Symbol VOH VOL VIH VIL VPP VCMR IIH Characteristic Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Minimum Input Swing Common Mode Range Input HIGH Current Min -1.3 -2.0 -1.1 -1.8 500 VCC -1.3V VCC -0.5V 150 Typ Max -0.7 -1.4 -0.9 -1.5 Min -1.3 -2.0 -1.1 -1.8 500 VCC -1.3V VCC -0.5V 150 25C Typ -1.0 -1.7 Max -0.7 -1.4 -0.9 -1.5 Min -1.3 -2.0 -1.1 -1.8 500 VCC -1.3V VCC -0.5V 150 240 70C Typ Max -0.7 -1.4 -0.9 -1.5 Unit V V V V mV V A mA
IGNDI Power Supply Current 200 240 200 240 200 1. Refer to Motorola Application Note AN1545/D "Thermal Data for MPC Clock Drivers" for thermal management guidelines.
PECL DC CHARACTERISTICS (TA = 0 to 70C, VCCA = VCCI = VCCO = 3.3V 5%, GNDI = 0V, Note 2.)
0C Symbol VOH VOL VIH VIL VPP VCMR IIH Characteristic Output HIGH Voltage (Note 3.) Output LOW Voltage (Note 3.) Input HIGH Voltage (Note 3.) Input LOW Voltage (Note 3.) Minimum Input Swing Common Mode Range Input HIGH Current Min 2.0 1.3 2.2 1.5 500 VCC -1.3V VCC -0.5V 150 Typ Max 2.6 1.9 2.4 1.8 Min 2.0 1.3 2.2 1.5 500 VCC -1.3V VCC -0.5V 150 25C Typ 2.3 1.6 Max 2.6 1.9 2.4 1.8 Min 2.3 1.3 2.2 1.5 500 VCC -1.3V VCC -0.5V 150 240 70C Typ Max 2.6 1.9 2.4 1.8 Unit V V V V mV V A mA
IGNDI Power Supply Current 200 240 200 240 200 2. Refer to Motorola Application Note AN1545/D "Thermal Data for MPC Clock Drivers" for thermal management guidelines. 3. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
AC CHARACTERISTICS (TA = 0 to 70C, VCCA = VCCI = VCCO = 3.3V 5%, Termination of 50 to VCC - 2.0V)
Symbol fxtal tr, tf tpw tos fVCO tpd fmax Characteristic Crystal Oscillator Frequency Output Rise/Fall Time Output Duty Cycle Output-to-Output Skew PLL VCO Lock Range Ref to Feedback Offset Maximum Output Frequency Qa,Qb,Qc (/2) Qa,Qb,Qc (/4) Qa,Qb,Qc (/6) Qa,Qb,Qc (/8) Cycle-to-Cycle Jitter (Peak-to-Peak) 50 Same Frequency Different Frequencies VCO_Sel = `0' VCO_Sel = `1' 400 200 75 250 Min 10 0.2 47.5 50 150 250 Typ Max 25 1.0 52.5 250 350 800 400 425 400 200 133 100 Unit MHz ns % ps MHz ps MHz FB /8 to /32 (Note 4.) FB /4 to /32 fref = 50MHz (Note 5.) 20% to 80% Condition
tjitter
ps
tlock Maximum PLL Lock Time 10 ms 4. With VCO_Sel = `0', the PLL will be unstable with a /2, /4 or /6 feedback ratio. With VCO_Sel = `1', the PLL will be unstable with a /2 feedback ratio. 5. tpd is specified for 50MHz input reference FB /8. The window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. The tpd does not include jitter.
TIMING SOLUTIONS BR1333 -- Rev 6
5
MOTOROLA
MPC990 MPC991
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70C)
Symbol tr, tf fref Characteristic TCLK Input Rise/Falls Reference Input Frequency Note 6. Min Max 3.0 Note 6. Unit ns MHz Condition
frefDC Reference Input Duty Cycle 25 75 % 6. Maximum and minimum input reference frequencies are limited by the VCO lock range and the feedback divider.
APPLICATIONS INFORMATION
Using the On-Board Crystal Oscillator The MPC990 features an on-board crystal oscillator to allow for seed clock generation as well as final distribution. The on-board oscillator is completely self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC990 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required. The oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this eliminates the need for large on-board capacitors. Because the design is a series resonant design for the optimum frequency accuracy a series resonant crystal should be used (see specification table below). Unfortunately most of the shelf crystals are characterized in a parallel resonant mode. However a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel resonant mode. Therefore in the majority of cases a parallel specified crystal can be used with the MPC990 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. Typically a parallel specified crystal used in a series resonant mode will exhibit an oscillatory frequency a few hundred ppm lower than the specified value. For most processor implementations a few hundred ppm translates into kHz inaccuracies, a level which does not represent a major issue. The MPC990 is a clock driver which was designed to generate outputs with programmable frequency relationships and not a synthesizer with a fixed input frequency. As a result the crystal input frequency is a function of the desired output frequency. For a design which utilizes the external feedback to the PLL the selection of the crystal frequency is straight forward; simply chose a crystal which is equal in frequency to the fed back signal. Table 1. Crystal Specifications
Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental at Cut Series Resonance* 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 Max 100W 5ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant discussion.
Power Supply Filtering The MPC990/991 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC990/991 provides separate power supplies for the output buffers (VCCO) and the internal PLL (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC990/991. Figure 4 illustrates a typical power supply filter scheme. The MPC990/991 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter
MOTOROLA
6
TIMING SOLUTIONS BR1333 -- Rev 6
MPC990 MPC991
should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC990/991. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 4 must have a resistance of 5-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC990/991 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
3.3V
RS=5-15 VCCA 22F MPC990/991 VCC 0.01F 0.01F
Figure 4. Power Supply Filter
TIMING SOLUTIONS BR1333 -- Rev 6
7
MOTOROLA
MPC990 MPC991
OUTLINE DIMENSIONS
FA SUFFIX TQFP PACKAGE CASE 848D-03 ISSUE C
C L
4X 4X TIPS
-X- X=L, M, N
AB AB
G
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N
52 1
40 39
VIEW Y F
BASE METAL
3X VIEW
Y -M- B V
PLATING
J
B1
13 14 26 27
V1
0.13 (0.005)
SECTION AB-AB
ROTATED 90_ CLOCKWISE
A1 S1 A S
-N-
C -H- -T-
SEATING PLANE
4X
2 0.10 (0.004) T
4X
3 VIEW AA
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.75 0.45 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _
0.05 (0.002)
S
W 1 C2
2XR
R1
0.25 (0.010)
GAGE PLANE
K C1 E Z VIEW AA
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
MOTOROLA
8
CCCC EEEE CCCC EEEE
M
-L-
U
D T L-M
S
N
S
TIMING SOLUTIONS BR1333 -- Rev 6
MPC990 MPC991
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TIMING SOLUTIONS BR1333 -- Rev 6
9
MPC990/D MOTOROLA

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